1. Field
The general inventive concept relates to a tester configured to test a semiconductor device and a test system including the tester, and more particularly, to a tester including a memory controller connected between a host and a semiconductor device and capable of testing the semiconductor device and a test system including the tester.
2. Description of the Related Art
A test process for determining whether a semiconductor device is good or defective may be greatly classified into a wafer-level test and a final test. The wafer-level test may be performed on individual semiconductor dies on a wafer level, while the final test may be performed on a semiconductor package in which individual semiconductor dies are packaged. Although the test process requires expensive tester equipment, a parallel test may be restricted by the number of channels of a tester. In particular, with an increase in the density of semiconductor devices and a rise in the demand for multichip packages (MCPs), test costs may be greatly increased